Binary package “yosys-abc” in ubuntu noble
Sequential Logic Synthesis and Verification Algorithms
ABC is a system for synthesis and verification of binary sequential logic
circuits appearing in synchronous hardware designs. It combines scalable
logic optimization based on And-Inverter Graphs (AIGs), optimal-delay
DAG-based technology mapping for look-up tables and standard cells, and
innovative algorithms for sequential synthesis and verification.
.
This is a fork of berkeley-abc maintained by the YosysHQ team for use in
the yosys RTL synthesis framework.
Source package
Published versions
- yosys-abc 0.33-5build2 in amd64 (Proposed)
- yosys-abc 0.33-5build2 in amd64 (Release)
- yosys-abc 0.33-5build2 in arm64 (Proposed)
- yosys-abc 0.33-5build2 in arm64 (Release)
- yosys-abc 0.33-5build2 in armhf (Proposed)
- yosys-abc 0.33-5build2 in armhf (Release)
- yosys-abc 0.33-5build2 in ppc64el (Proposed)
- yosys-abc 0.33-5build2 in ppc64el (Release)
- yosys-abc 0.33-5build2 in riscv64 (Proposed)
- yosys-abc 0.33-5build2 in riscv64 (Release)
