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yosys package

yosys 0.33-5build2 source package in Ubuntu

Changelog

yosys (0.33-5build2) noble; urgency=medium

  * No-change rebuild for CVE-2024-3094

 -- William Grant <email address hidden>  Mon, 01 Apr 2024 15:53:45 +1100

Upload details

Uploaded by:
William Grant
Uploaded to:
Noble
Original maintainer:
Ubuntu Developers
Architectures:
any all
Section:
misc
Urgency:
Medium Urgency

See full publishing history Publishing

Series Pocket Published Component Section
Oracular release universe misc
Noble release universe misc

Downloads

File Size SHA-256 Checksum
yosys_0.33.orig-abc.tar.gz 5.9 MiB 6559115f2bbf4f1aac86ae4edbae416e8c60b8998bb3ac552451f4283bf6a5a7
yosys_0.33.orig.tar.gz 2.5 MiB c240fa4fcc71c73b8989ab500f7bfa3109436fa1d7ba8d7e1028af4c42688f29
yosys_0.33-5build2.debian.tar.xz 29.5 KiB 704b00f0302d1806c569d4a0f73029dfc436c6e7e928b377b06ac36de9d80982
yosys_0.33-5build2.dsc 3.0 KiB 538743309f336b70406401d5edcb2c224d2b6eca5114f01ae8ee9691098a9c84

Available diffs

View changes file

Binary packages built by this source

yosys: Framework for Verilog RTL synthesis

 This is a framework for Verilog RTL synthesis. It currently has extensive
 Verilog-2005 support and provides a basic set of synthesis algorithms for
 various application domains.
 .
 Yosys can be adapted to perform any synthesis job by combining the existing
 passes (algorithms) using synthesis scripts and adding additional passes as
 needed by extending the yosys C++ code base.

yosys-abc: Sequential Logic Synthesis and Verification Algorithms

 ABC is a system for synthesis and verification of binary sequential logic
 circuits appearing in synchronous hardware designs. It combines scalable
 logic optimization based on And-Inverter Graphs (AIGs), optimal-delay
 DAG-based technology mapping for look-up tables and standard cells, and
 innovative algorithms for sequential synthesis and verification.
 .
 This is a fork of berkeley-abc maintained by the YosysHQ team for use in
 the yosys RTL synthesis framework.

yosys-abc-dbgsym: debug symbols for yosys-abc
yosys-dbgsym: debug symbols for yosys
yosys-dev: Framework for Verilog RTL synthesis (development files)

 Yosys is a framework for Verilog RTL synthesis. It currently has extensive
 Verilog-2005 support and provides a basic set of synthesis algorithms for
 various application domains.
 .
 Yosys can be adapted to perform any synthesis job by combining the existing
 passes (algorithms) using synthesis scripts and adding additional passes as
 needed by extending the yosys C++ code base.
 .
 This package contains the headers and programs needed to build yosys plugins.

yosys-doc: Framework for Verilog RTL synthesis (documentation)

 Yosys is a framework for Verilog RTL synthesis. It currently has extensive
 Verilog-2005 support and provides a basic set of synthesis algorithms for
 various application domains.
 .
 Yosys can be adapted to perform any synthesis job by combining the existing
 passes (algorithms) using synthesis scripts and adding additional passes as
 needed by extending the yosys C++ code base.
 .
 This package contains the manual.