yosys-abc 0.33-5build2 (arm64 binary) in ubuntu noble

 ABC is a system for synthesis and verification of binary sequential logic
 circuits appearing in synchronous hardware designs. It combines scalable
 logic optimization based on And-Inverter Graphs (AIGs), optimal-delay
 DAG-based technology mapping for look-up tables and standard cells, and
 innovative algorithms for sequential synthesis and verification.
 .
 This is a fork of berkeley-abc maintained by the YosysHQ team for use in
 the yosys RTL synthesis framework.