I'm glad you have 7713 and 7763 that is great for our joint testing.
I have to state that "my" 7713 have erms and are thereby happy to start
with the EPYC-Milan type.
fsrm I agree, that had to be disabled
<feature policy='disable' name='fsrm'/>
While that is great (new named model, extra named features to specify)
there is a sad point left, for me I still get MSR errors in the guest.
Apr 15 10:46:08 h-on-f kernel: unchecked MSR access error: WRMSR to 0xda0 (tried to write 0x0000000000000000) at rIP: 0xffffffff9907fa44 (native_write_msr+0x4/0x30)
Apr 15 10:46:08 h-on-f kernel: unchecked MSR access error: RDMSR from 0xda0 at rIP: 0xffffffff9907f968 (native_read_msr+0x8/0x40)
The same is true for the new EPYC-Rome-v2 type.
If I manually add IBRS like:
<cpu mode='custom' match='exact' check='full'>
<model fallback='forbid'>EPYC-Rome</model>
<feature policy='require' name='ibrs'/>
</cpu>
It still trigger the same MSR issue.
But then - just as you said - this is an engineering example.
I even have scary ECC warnings every now and then.
So I'd really be interested for an explicit double check on your 7763 chips.
I'm glad you have 7713 and 7763 that is great for our joint testing.
I have to state that "my" 7713 have erms and are thereby happy to start
with the EPYC-Milan type.
fsrm I agree, that had to be disabled
<feature policy='disable' name='fsrm'/>
Full CPU definition 'forbid' >EPYC-Milan< /model> addr-chk' />
<cpu mode='custom' match='exact' check='full'>
<model fallback=
<feature policy='require' name='x2apic'/>
<feature policy='require' name='hypervisor'/>
<feature policy='disable' name='invpcid'/>
<feature policy='disable' name='pku'/>
<feature policy='disable' name='fsrm'/>
<feature policy='require' name='topoext'/>
<feature policy='disable' name='svme-
</cpu>
While that is great (new named model, extra named features to specify)
there is a sad point left, for me I still get MSR errors in the guest.
Apr 15 10:46:08 h-on-f kernel: unchecked MSR access error: WRMSR to 0xda0 (tried to write 0x0000000000000000) at rIP: 0xffffffff9907fa44 (native_ write_msr+ 0x4/0x30) read_msr+ 0x8/0x40)
Apr 15 10:46:08 h-on-f kernel: unchecked MSR access error: RDMSR from 0xda0 at rIP: 0xffffffff9907f968 (native_
The same is true for the new EPYC-Rome-v2 type.
If I manually add IBRS like: 'forbid' >EPYC-Rome< /model>
<cpu mode='custom' match='exact' check='full'>
<model fallback=
<feature policy='require' name='ibrs'/>
</cpu>
It still trigger the same MSR issue.
But then - just as you said - this is an engineering example.
I even have scary ECC warnings every now and then.
So I'd really be interested for an explicit double check on your 7763 chips.