Comment 8 for bug 746178

Hi Luis-

Unfortunately, we do not currently have any such tests for the DRC. The
problem is that we don't currently have a way of writing the output of the
DRC to a file. This makes it difficult to run an automatic regression test
with our current testing framework. Producing such output is on my todo
list! Having the input files ready will be a big help when I get there.

The pcb test suite is an area that could use a substantial development
effort. I've been trying to create new tests as I work through other
problems, but this is a slow process and it is far from complete.
Consequently, all contributions are welcome!

Thanks,
--Chad

On Tue, Jul 10, 2018 at 4:25 AM, Luis de Arquer <email address hidden>
wrote:

> Hi Chad,
>
> OK, I'll get them.
> Do you have some other DRC test files? So I can test there are no
> regressions with this patch?
>
> Luis
>
> --
> You received this bug notification because you are subscribed to the bug
> report.
> https://bugs.launchpad.net/bugs/746178
>
> Title:
> Polygon to line separation DRC wrong
>
> Status in gEDA project:
> New
> Status in pcb:
> In Progress
>
> Bug description:
> DRC incorrectly complains about the clearance between polygon and line
> in the attached PCB.
> With minclear set to 3.98mil DRC complains, even though the separation
> is about 4.5mil.
> PCB version is GIT head fetched on 20110329, patched with Peter
> Clifton's patch for bug 746093
>
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