Polygon to line separation DRC wrong

[Stephen Ecob]

DRC incorrectly complains about the clearance between polygon and line in the attached PCB.
With minclear set to 3.98mil DRC complains, even though the separation is about 4.5mil.
PCB version is GIT head fetched on 20110329, patched with Peter Clifton's patch for bug 746093

[Luis de Arquer (ldearquer)]

I have been stumbling with DRC issues which could be reduced to the same problem, even with latest master as of 07/2018 (commit 475c79598)
The reason why this happens is that, when the track is considered to plow through the polygon, only the clearance of the line is taken into account, not the real distance to the polygon.

if (line->Clearance < 2 * PCB->Bloat)
{
  AddObjectToFlagUndoList (type, ptr1, ptr2, ptr2);
  SET_FLAG (i->flag, line);
  message = _("Line with insufficient clearance inside polygon\n");
  goto doIsBad;
}

But PlowsPolygon() uses the bounding box of the line, which is not very accurate, rendering some false positives. The function IsLineInPolygon(), though, performs an accurate, though more expensive, test.

If we use IsLineInPolygon() with the "candidates" detected by PlowsPolygon(), the bug is fixed. Also, it fixed other related bugs (for example, when the plowing line has low clearance, but still is far from the polygon because other elements of higher clearance plow the polygon at the same place too).

[Luis de Arquer (ldearquer)]

diff --git a/src/find.c b/src/find.c
index 3382c3c..2d94166 100644
--- a/src/find.c
+++ b/src/find.c
@@ -3597,12 +3597,35 @@ drc_callback (DataType *data, LayerType *layer, PolygonType *polygon,
     {
     case LINE_TYPE:
       if (line->Clearance < 2 * PCB->Bloat)
- {
- AddObjectToFlagUndoList (type, ptr1, ptr2, ptr2);
- SET_FLAG (i->flag, line);
- message = _("Line with insufficient clearance inside polygon\n");
- goto doIsBad;
- }
+ {
+ /*
+ * PlowsPolygon made a weak check (bounding box) of whether
+ * the line plows through the polygon, throwing some false
+ * positives. Here we bloat the line and use IsLineInPolygon()
+ * to rule out the false positives.
+ * To use it, we need to clear CLEARLINEFLAG, and restore it later
+ * XXX We could assume it is always set, to simplify this code?
+ * (PlowsPolygon requires it)...
+ */
+ int clearflag;
+ bool is_line_in_polygon;
+
+ clearflag = TEST_FLAG (CLEARLINEFLAG, line);
+ CLEAR_FLAG (CLEARLINEFLAG, line);
+ Bloat = 2*PCB->Bloat;
+ is_line_in_polygon = IsLineInPolygon(line,polygon);
+ Bloat = 0;
+ if (clearflag)
+ SET_FLAG (CLEARLINEFLAG, line);
+
+ if (is_line_in_polygon)
+ {
+ AddObjectToFlagUndoList (type, ptr1, ptr2, ptr2);
+ SET_FLAG (i->flag, line);
+ message = _("Line with insufficient clearance inside polygon\n");
+ goto doIsBad;
+ }
+ }
       break;
     case ARC_TYPE:
       if (arc->Clearance < 2 * PCB->Bloat)

[Luis de Arquer (ldearquer)]

This same fix could be used for arc, but I haven't tested it yet...

[Chad Parker (parker-charles)]

Hi Luis-

Thanks for your patch.

You mentioned some other cases that this patch fixes. Could you please create a pcb file that demonstrates all the cases you know of? I'd like to put together some automated tests to prevent future regression.

If this problem affects other types as well, such as arcs as you've suggested, we should fix those and include them in the patch as well.

Thank you,
--Chad

[Stephen Ecob (silicon-on-inspiration)]

Thanks for the patch Luis !
Best regards,
Stephen

[Luis de Arquer (ldearquer)]

Hi Chad,

OK, I'll get them.
Do you have some other DRC test files? So I can test there are no regressions with this patch?

Luis

[Chad Parker (parker-charles)]

Hi Luis-

Unfortunately, we do not currently have any such tests for the DRC. The
problem is that we don't currently have a way of writing the output of the
DRC to a file. This makes it difficult to run an automatic regression test
with our current testing framework. Producing such output is on my todo
list! Having the input files ready will be a big help when I get there.

The pcb test suite is an area that could use a substantial development
effort. I've been trying to create new tests as I work through other
problems, but this is a slow process and it is far from complete.
Consequently, all contributions are welcome!

Thanks,
--Chad

On Tue, Jul 10, 2018 at 4:25 AM, Luis de Arquer <email address hidden>
wrote:

> Hi Chad,
>
> OK, I'll get them.
> Do you have some other DRC test files? So I can test there are no
> regressions with this patch?
>
> Luis
>
> --
> You received this bug notification because you are subscribed to the bug
> report.
> https://bugs.launchpad.net/bugs/746178
>
> Title:
> Polygon to line separation DRC wrong
>
> Status in gEDA project:
> New
> Status in pcb:
> In Progress
>
> Bug description:
> DRC incorrectly complains about the clearance between polygon and line
> in the attached PCB.
> With minclear set to 3.98mil DRC complains, even though the separation
> is about 4.5mil.
> PCB version is GIT head fetched on 20110329, patched with Peter
> Clifton's patch for bug 746093
>
> To manage notifications about this bug go to:
> https://bugs.launchpad.net/geda-project/+bug/746178/+subscriptions
>

[Chad Parker (parker-charles)]

Hi Luis-

I've "assigned" you to this bug so that you can more clearly get the credit for fixing it. I can change that if you object.

Thanks,
--Chad

[Luis de Arquer (ldearquer)]

Hi Chad,

No problem, thanks.
I may look around and flag the other bugs fixed with this (and the other) patch.

2018-07-16 14:38 GMT+02:00, Chad Parker <email address hidden>:
> Hi Luis-
>
> I've "assigned" you to this bug so that you can more clearly get the
> credit for fixing it. I can change that if you object.
>
> Thanks,
> --Chad
>
> ** Changed in: pcb
> Importance: Undecided => High
>
> ** Changed in: pcb
> Assignee: (unassigned) => Luis de Arquer (ldearquer)
>
> --
> You received this bug notification because you are subscribed to the bug
> report.
> https://bugs.launchpad.net/bugs/746178
>
> Title:
> Polygon to line separation DRC wrong
>
> Status in gEDA project:
> New
> Status in pcb:
> In Progress
>
> Bug description:
> DRC incorrectly complains about the clearance between polygon and line in
> the attached PCB.
> With minclear set to 3.98mil DRC complains, even though the separation is
> about 4.5mil.
> PCB version is GIT head fetched on 20110329, patched with Peter Clifton's
> patch for bug 746093
>
> To manage notifications about this bug go to:
> https://bugs.launchpad.net/geda-project/+bug/746178/+subscriptions
>