I have attached a patch that explicitly disables the L2 cache on boot, but I have observed issues with it that would need to be tracked down if not resolved by the below:.
Additionally, I think UEFI should also assert L2BYPASS in the init code, ensuring the PL310 is completely disabled. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0448g/CHDJFEJC.html documents how this can be done in CFGRW1.
I have attached a patch that explicitly disables the L2 cache on boot, but I have observed issues with it that would need to be tracked down if not resolved by the below:.
Additionally, I think UEFI should also assert L2BYPASS in the init code, ensuring the PL310 is completely disabled. infocenter. arm.com/ help/index. jsp?topic= /com.arm. doc.dui0448g/ CHDJFEJC. html documents how this can be done in CFGRW1.
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