UEFI: VExpress 4xA9 support not bindings compliant

[Leif Lindholm]

I have found two issues with the VExpress 4xCortex-A9 port:
- The PL310 L2 cache controller is enabled by the init code, so you end up in a really bad state after you disable the MMU .
- ExitBootServices() does not mask interrupts (set CPSR I/F bits).

[Leif Lindholm (leif-lindholm)]

The attached patch makes the GIC driver disable IRQ/FIQ in the core on ExitBootServices().

[Leif Lindholm (leif-lindholm)]

I have attached a patch that explicitly disables the L2 cache on boot, but I have observed issues with it that would need to be tracked down if not resolved by the below:.

Additionally, I think UEFI should also assert L2BYPASS in the init code, ensuring the PL310 is completely disabled.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0448g/CHDJFEJC.html documents how this can be done in CFGRW1.

[Leif Lindholm (leif-lindholm)]

Second part is now resolved upstream.

Assigning to Ryan to verify first part.

[Ryan Harkin (ryanharkin)]

ACTION: Ryan to check if PL310 L2 cache controller is still initialised in the A9 BSP

[Ryan Harkin (ryanharkin)]

In ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibCTA9x4/CTA9x4Sec.c, function ArmPlatformSecInitialize does this:

  // The L2x0 controller must be intialize in Secure World
  L2x0CacheInit(PcdGet32(PcdL2x0ControllerBase),
      PL310_TAG_LATENCIES(L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES),
      PL310_DATA_LATENCIES(L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES),
      0,~0, // Use default setting for the Auxiliary Control Register
      FALSE);

So I guess it's still not "bindings compliant"

[Ilias Biris (ibiris)]

If the remaining issue is still a problem for anyone (assuming everyone else is using TC2 now) then let us know - marking as won't fix overall.