Comment 8 for bug 1839822

Hi Ken,

1) The bus labels/ports being blue now is intentional. This behavior is new compared to 5.x

2) The ERC warnings in your screenshot are a bug, I will fix it

3) As JP mentioned, the generated netlist is correct so your PCB should be correct

4) As Michael mentioned, highlighting also seems to be broken between sheets at the moment, that was working a while ago but I've been out of the loop for a few months so this could be any number of things.