Hierarchical Bus not working in latest nightlies

[Ken Lowe]

Unfortunately, I uninstalled the latest nightly, and reverted back to 5.1.4_1, so I don't have the complete version information. However, I can advise that it was kicad-r13978.e04436b13-x86_64.exe dated 10/08/19 from the nightly builds that I installed and had a problem with. This is installed in a Windows 10 x64 environment.

The issue I am having is that hierarchical busses don't seem to feed through into other sheets correctly. I don’t know if the colour of the bus pin is a clue to what’s going wrong. It’s no longer the same yellowish colour as the individual hierarchical line pins. The bus pins are now blue. The ERC errors state that ‘Label not connected anywhere else in the schematic’. Any idea what might be going wrong?

Please see detail here:

https://forum.kicad.info/t/hierarchical-bus-in-latest-nightlies/18444

This problem doesn't exist on version 5.1.4_2.

Thanks

[Wayne Stambaugh (stambaughw)]

Not sure but I'm guessing this is related to https://bugs.launchpad.net/kicad/+bug/1831594.

[Michael Kavanagh (michaelkavanagh)]

Can you upload an example project which exhibits this issue?

[Ken Lowe (chaser2001)]

As requested...

Firstly, I created a new project in stable release Kicad 5.1.4_1. See attached archive 5.1.4_1.zip. I've included full details of Kicad version in the archive, and also a screen shot of the ERC test. This version worked fine.

I then downloaded and installed latest nightly kicad-r14024.a0eaff289-x86_64.exe and opened up the above project which was created in Kicad 5.1.4_1. See attached archive LatestNightly.zip. Again, I've included full details of Kicad version in the archive, and also a screen shot of the ERC test. This time it has failed with a number of errors that 'Label..... is not connected anywhere else in the schematic' for the hierarchical pins.

[Michael Kavanagh (michaelkavanagh)]

If I have interpreted this correctly, schematics created in 5.1 with buses routed through hierarchical sheet pins no longer connect outside their sheet in master? I am seeing broken bus connections between the two hierarchical sheets in 6.0 but not in 5.1.4.

Please correct me if I am wrong. There have been a lot of changes in this area that I haven't kept fully up to speed on.

[jean-pierre charras (jp-charras)]

No problem with the netlist.

It looks to me this is just a DRC overzealous warning:
A unique bus label in a sheet is a usual case.
This warning is OK for a usual local label, nor for a bus label, that is frequently unique in a sheet.

[Ken Lowe (chaser2001)]

@michaelkavanagh - Your interpretation is correct on the schematic. I've not tried reading the netlist in PCBNew to see if it's just a schematic issue, or a more fundamental netlist issue, but @jp-charras is indicating that it's just a schematic and ERC issue.

[Michael Kavanagh (michaelkavanagh)]

I did test with the net highlight tool and the nets didn’t seem to connect between sheets.

[Jon Evans (craftyjon)]

Hi Ken,

1) The bus labels/ports being blue now is intentional. This behavior is new compared to 5.x

2) The ERC warnings in your screenshot are a bug, I will fix it

3) As JP mentioned, the generated netlist is correct so your PCB should be correct

4) As Michael mentioned, highlighting also seems to be broken between sheets at the moment, that was working a while ago but I've been out of the loop for a few months so this could be any number of things.

[Ken Lowe (chaser2001)]

Thank you Jon. I'll test at the next opportunity.