@michaelkavanagh - Your interpretation is correct on the schematic. I've not tried reading the netlist in PCBNew to see if it's just a schematic issue, or a more fundamental netlist issue, but @jp-charras is indicating that it's just a schematic and ERC issue.
@michaelkavanagh - Your interpretation is correct on the schematic. I've not tried reading the netlist in PCBNew to see if it's just a schematic issue, or a more fundamental netlist issue, but @jp-charras is indicating that it's just a schematic and ERC issue.