Comment 2 for bug 1827905

We've made some changes to the schematic, which need to be reflected in the PCB netlist.

But for the ram, we didn't change the schematics; the electrical connection should be the same.

Let's say we have;

padA-trackA-padB
netA-netA-netA

what's happened is that now I have;

padA-trackA-padB
netA-netA-netC

And netC isn't connected to netA.

But schematically, netA and netC are the same net. Also, the netname doesn't seem like it has it's proper hierarchy anymore. The orphan pad is called, "/A7", and the pad it's wired to is, "/A_MemA7".

"/A7" is inside a sheet, and it does properly connect to all the other DDR4 ICs in that sheet. But it doesn't connect from within that sheet to the FPGA.

It seems like the netlist generator isn't making the connection from within the sheet and the local netnames and the connection to a higher level sheet.

If I follow the net name, I have to go up three sheets, and then back down into two more sheets from the top level sheet.

I am not sure why it's not doing that because they are connected.