PCBnew/EESchema: Net naming convention breaks older designs.

Bug #1827905 reported by Madeliene Kattman
6
This bug affects 1 person
Affects Status Importance Assigned to Milestone
KiCad
Fix Committed
Medium
Jon Evans

Bug Description

We're migrating our pcb design from kicad 5.1 to the current nightly. However, it looks like the newer version of kicad resolves netnames differently than 5.1.

We have a very large hierarchical design (>110 sheets, 5k nets).

When using the hierarchical sheets, and importing the new design, kicad seems to be changing how it determines netnames from hierarchies.

This is causing the pads to have a new netname that is different than the original netname for the various traces. This is especially true for our modular design.

This makes it really hard to do layout because then I would have to reroute or reassign all the nets that have changed, and this is happening across all our DDR4 ram blocks!!

Is there a way to make the traces infer their netnames based on the connected lands? Or else have the netname inferred in the same way older versions did?

Tags: eeschema
Revision history for this message
Jon Evans (craftyjon) wrote :

Hi Madeliene,

There have been some changes made to the way net names are determined in order to make the system more predictable and enable new features. However, this change is fairly new and it is possible there are still bugs in it.

Can you please share details about what changes occurred, and what the desired behavior is for you? I will check to see if an improvement is possible. If you are able to share your design privately with me it will help speed up fixing this. If not, some more detailed description of an example change will help.

Also, to be clear, are you saying that the net names have changed (but the connection between pads is still the same) or that the actual connections have also changed? In other words, when you import the netlist from schematic into PcbNew, do connections break / new ratsnest lines appear? If that's the case, this is a different problem.

Thanks

Changed in kicad:
assignee: nobody → Jon Evans (craftyjon)
milestone: none → 6.0.0-rc1
importance: Undecided → Medium
status: New → Incomplete
tags: added: eeschema
Revision history for this message
Madeliene Kattman (katm) wrote :

We've made some changes to the schematic, which need to be reflected in the PCB netlist.

But for the ram, we didn't change the schematics; the electrical connection should be the same.

Let's say we have;

padA-trackA-padB
netA-netA-netA

what's happened is that now I have;

padA-trackA-padB
netA-netA-netC

And netC isn't connected to netA.

But schematically, netA and netC are the same net. Also, the netname doesn't seem like it has it's proper hierarchy anymore. The orphan pad is called, "/A7", and the pad it's wired to is, "/A_MemA7".

"/A7" is inside a sheet, and it does properly connect to all the other DDR4 ICs in that sheet. But it doesn't connect from within that sheet to the FPGA.

It seems like the netlist generator isn't making the connection from within the sheet and the local netnames and the connection to a higher level sheet.

If I follow the net name, I have to go up three sheets, and then back down into two more sheets from the top level sheet.

I am not sure why it's not doing that because they are connected.

Revision history for this message
Jon Evans (craftyjon) wrote :

Ok, then that is indeed a connectivity bug and I will work on fixing it. Can you please paste the output of About->Copy Version Info?

If you are able to share your design confidentially with me by email, please do so. I will use it to test that the bug has been fixed. If not, I will try to reproduce some other way.

Revision history for this message
Madeliene Kattman (katm) wrote :

Application: kicad
Version: (5.1.0-386-g9f189ca71), release build
Libraries:
    wxWidgets 3.0.4
    libcurl/7.64.0 OpenSSL/1.1.1b zlib/1.2.11 libidn2/2.1.1 libpsl/0.20.2 (+libidn2/2.1.1) libssh2/1.8.1 nghttp2/1.36.0
Platform: Linux 5.0.4-arch1-1-ARCH x86_64, 64 bit, Little endian, wxGTK
Build Info:
    wxWidgets: 3.0.4 (wchar_t,wx containers,compatible with 2.8) GTK+ 2.24
    Boost: 1.69.0
    OpenCASCADE Community Edition: 6.9.1
    Curl: 7.64.0
    Compiler: GCC 8.2.1 with C++ ABI 1013

Build settings:
    USE_WX_GRAPHICS_CONTEXT=OFF
    USE_WX_OVERLAY=OFF
    KICAD_SCRIPTING=ON
    KICAD_SCRIPTING_MODULES=ON
    KICAD_SCRIPTING_PYTHON3=OFF
    KICAD_SCRIPTING_WXPYTHON=OFF
    KICAD_SCRIPTING_WXPYTHON_PHOENIX=OFF
    KICAD_SCRIPTING_ACTION_MENU=ON
    BUILD_GITHUB_PLUGIN=ON
    KICAD_USE_OCE=ON
    KICAD_USE_OCC=OFF
    KICAD_SPICE=ON

Revision history for this message
Madeliene Kattman (katm) wrote :

Sent direct message re: sharing design.

Jon Evans (craftyjon)
Changed in kicad:
status: Incomplete → Confirmed
Jon Evans (craftyjon)
Changed in kicad:
status: Confirmed → In Progress
Revision history for this message
Jon Evans (craftyjon) wrote :

This issue has been noted as resolved by Madeliene after recent commits

Changed in kicad:
status: In Progress → Fix Committed
To post a comment you must log in.
This report contains Public information  
Everyone can see this information.

Other bug subscribers

Remote bug watches

Bug watches keep track of this bug in other bug trackers.