@Holger,
First, thanks for all your work on ngspice and your help for Kicad.
Creating a netlist entry for XU1n in1 in2 out VCC GND for each n unit is (easily?) feasible, as long as each unit has 5 pins.
However the main issue in current libraries (It was not the case for old libs with invisible power pins) is the fact each unit has 3 pins, not 5 (they do not have any power pins).
A specific units handles the power pins.
Solving this problem is not easy, and will be possible only after significant changes in Eeschema internals, ERC and netlist generation, unless using a library specific to spice simulation.
OTOH, this problem:
"Creating another ngspice model with all 14 nodes (4 x NAND, VCC, GND), as the 74HC00 IC offers, is not an alternative. The resulting subcircuit would then require having always all for gates connected, otherwise there would be a mismatch between the nodes required by the circuit and the ones offered by the subcircuit"
is not so critical:
If a package has 4 units, all should appear in the schematic, because:
- in many cases unused pins cannot be left open (especially in CMOS logic).
- it is always good to clearly show the unused units, for readers.
@Holger,
First, thanks for all your work on ngspice and your help for Kicad.
Creating a netlist entry for XU1n in1 in2 out VCC GND for each n unit is (easily?) feasible, as long as each unit has 5 pins.
However the main issue in current libraries (It was not the case for old libs with invisible power pins) is the fact each unit has 3 pins, not 5 (they do not have any power pins).
A specific units handles the power pins.
Solving this problem is not easy, and will be possible only after significant changes in Eeschema internals, ERC and netlist generation, unless using a library specific to spice simulation.
OTOH, this problem:
"Creating another ngspice model with all 14 nodes (4 x NAND, VCC, GND), as the 74HC00 IC offers, is not an alternative. The resulting subcircuit would then require having always all for gates connected, otherwise there would be a mismatch between the nodes required by the circuit and the ones offered by the subcircuit"
is not so critical:
If a package has 4 units, all should appear in the schematic, because:
- in many cases unused pins cannot be left open (especially in CMOS logic).
- it is always good to clearly show the unused units, for readers.