Cannot simulate multipart devices

Bug #1781290 reported by Holger Vogt on 2018-07-11
6
This bug affects 1 person
Affects Status Importance Assigned to Milestone
KiCad
Low
Unassigned

Bug Description

Using Eeschema and ngspice.
Example is an inverter chain with 74HC00 from 74xx library. The 74HC00 has four 2-input NAND gates in one IC package.
When adding this to a circuit, e.g. a simple inverter chain, I may use the symbols U1A, U1B, U1C, U1D (the 4 NAND gates), U1E (VCC, GND). The (home made) ngspice library model contains a NAND gate with nodes in1, in2, out, VCC, GND.

Next is to instantiate each of the symbols (U1A - U1D) by double click on the symbol to open the 'Symbol Properties' window, then selecting the Spice Model Editor to enter the ngspice library path, subcircuit type, model (74HC00) and alternate node sequence, e.g. 4 5 6 14 7 for U1B.

Running the simulation and watching the netlist, only a single subcircuit
XU1 /in1 /in1 Net-_U1-Pad3_ VCC 0 74HC00
from U1A with its 5 nodes is created, U1B to U1D are not recognized.

Instead we would need 4 subcircuit instantiations
XU1A
XU1B
XU1C
XU1D
each with its 5 nodes (in1 in2 out VCC GND), with the common Spice model and individual alternate node sequences.

Creating another ngspice model with all 14 nodes (4 x NAND, VCC, GND), as the 74HC00 IC offers, is not an alternative. The resulting subcircuit would then require having always all for gates connected, otherwise there would be a mismatch between the nodes required by the circuit and the ones offered by the subcircuit.

Taking each NAND gate from another unit (U1A, U2A, U3A, U4A) will allow the simulation, but of course this is not acceptable if a PCB is designed.

Application: eeschema
Version: (5.0.0-rc3-dev-2-g101b68b61), release build
Libraries:
    wxWidgets 3.0.3
    libcurl/7.54.1 OpenSSL/1.0.2l zlib/1.2.11 libssh2/1.8.0 nghttp2/1.23.1 librtmp/2.3
Platform: Windows 7 (build 7601, Service Pack 1), 64-bit edition, 64 bit, Little endian, wxMSW
Build Info:
    wxWidgets: 3.0.3 (wchar_t,wx containers,compatible with 2.8)
    Boost: 1.60.0
    OpenCASCADE Community Edition: 6.8.0
    Curl: 7.54.1
    Compiler: GCC 7.1.0 with C++ ABI 1011

Build settings:
    USE_WX_GRAPHICS_CONTEXT=OFF
    USE_WX_OVERLAY=OFF
    KICAD_SCRIPTING=ON
    KICAD_SCRIPTING_MODULES=ON
    KICAD_SCRIPTING_WXPYTHON=ON
    KICAD_SCRIPTING_ACTION_MENU=ON
    BUILD_GITHUB_PLUGIN=ON
    KICAD_USE_OCE=ON
    KICAD_USE_OCC=OFF
    KICAD_SPICE=ON

tags: added: ngspice
tags: added: eeschema

@Holger,
First, thanks for all your work on ngspice and your help for Kicad.

Creating a netlist entry for XU1n in1 in2 out VCC GND for each n unit is (easily?) feasible, as long as each unit has 5 pins.

However the main issue in current libraries (It was not the case for old libs with invisible power pins) is the fact each unit has 3 pins, not 5 (they do not have any power pins).
A specific units handles the power pins.

Solving this problem is not easy, and will be possible only after significant changes in Eeschema internals, ERC and netlist generation, unless using a library specific to spice simulation.

OTOH, this problem:
"Creating another ngspice model with all 14 nodes (4 x NAND, VCC, GND), as the 74HC00 IC offers, is not an alternative. The resulting subcircuit would then require having always all for gates connected, otherwise there would be a mismatch between the nodes required by the circuit and the ones offered by the subcircuit"
is not so critical:

If a package has 4 units, all should appear in the schematic, because:
- in many cases unused pins cannot be left open (especially in CMOS logic).
- it is always good to clearly show the unused units, for readers.

Wayne Stambaugh (stambaughw) wrote :

@Holger, unfortunately this is a side effect of changing our logic (and op-amp) symbols from having power pins on every unit to having a separate unit for just the power pins. Your best bet is to checkout the old logic and op-amp symbol libraries or create your own symbol libraries. If all goes as planned, the new symbol file format will allow for using separate power pin units and still generate a valid spice netlist. Sorry about the hassle. Changing the symbols resolved the hidden pins issues which most users didn't like but it created the problem you are experiencing.

Changed in kicad:
status: New → Triaged
importance: Undecided → Low
milestone: none → 6.0.0-rc1
Bob Cousins (bobcousins42) wrote :

The spice simulation already requires special symbol, not least for GND, so it is not unreasonable to have special logic symbols for simulation.

I could quite easily generate a new set of symbols using symgen. However, it is simpler to use the "old" library symbols.

Anyway, there are workarounds for the library symbols, the main problem is that KiCad does not generate separate simulation units for each gate, that is not something users can workaround.

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