Comment 0 for bug 1704083

The problem is in multi-gate components, which has some pins common to two or more gates. It can be two buffers with common Enable pin, four diodes with common anode pin or (in my case) MCU with all GPIOs shown in one gate while same pins acting as USART I/Os shown in another gate.

Two years ago all wires connected to those common pins in different gates had the same net name e.g. was connected together as it takes place on PCB - all routes to same pin had same net name. I suppose this behavior was correct one.

Today's kicad netlist generator assigns separate net to every pin occurrence in gates. And at netlist loading phase only first pin occurrence is taken into account while all other connections to same pin in other gates _silently_ ignored, e.g. pin connection depends on gate numbering in package or even gates location on schematics sheet or possibly even it's edit order in time.

I'll try to show it using four Zenner diodes in sot23-5 package (ESDA6v1-SC5) has common anode on pin 2 and cathodes on pins 1,3,4,5.

Attached file bug-example1.sch where pin 2 of gate A is connected to GND power symbol while all othes pins left unconnected produces netlist, which after loading into bug-example.kicad_pcb shows correct connection of footprint pin 2 to net GND.

Attached file bug-example1.sch where pin 2 of gate B is connected to GND power symbol while all othes pins left unconnected produces netlist, which after loading into bug-example.kicad_pcb shows incorrect connection of footprint pin 2 to net "Net-(VD1-Pad2)" while connection to GND simply discarded.