netlist generated incorrectly for shared pins (cf: multi-gate components)

Bug #1704083 reported by Sergey A. Borshch on 2017-07-13
This bug affects 4 people
Affects Status Importance Assigned to Milestone
Jon Evans

Bug Description

The problem is in multi-gate components, which has some pins common to two or more gates. It can be two buffers with common Enable pin, four diodes with common anode pin or (in my case) MCU with all GPIOs shown in one gate while same pins acting as USART I/Os shown in another gate.

Two years ago all wires connected to those common pins in different gates had the same net name e.g. was connected together as it takes place on PCB - all routes to same pin had same net name. I suppose this behavior was correct one.

Today's kicad netlist generator assigns separate net to every pin occurrence in gates. And at netlist loading phase only first pin occurrence is taken into account while all other connections to same pin in other gates _silently_ ignored, e.g. pin connection depends on gate numbering in package or even gates location on schematics sheet or possibly even it's edit order in time.

I'll try to show it using four Zenner diodes in sot23-5 package (ESDA6v1-SC5) has common anode on pin 2 and cathodes on pins 1,3,4,5.

Attached file bug-example1.sch where pin 2 of gate A is connected to GND power symbol while all othes pins left unconnected produces netlist, which after loading into bug-example.kicad_pcb shows correct connection of footprint pin 2 to net GND.

Attached file bug-example2.sch where pin 2 of gate B is connected to GND power symbol while all othes pins left unconnected produces netlist, which after loading into bug-example.kicad_pcb shows incorrect connection of footprint pin 2 to net "Net-(VD1-Pad2)" while connection to GND simply discarded.

Sergey A. Borshch (sb-sf) wrote :
Sergey A. Borshch (sb-sf) wrote :

Sorry, missed version info:

Application: eeschema
Version: (2017-07-09 revision d7a4fb7)-master, release build
Libraries: wxWidgets 3.0.2
Platform: Linux 4.4.0-83-generic x86_64, 64 bit, Little endian, wxGTK
- Build Info -
wxWidgets: 3.0.2 (wchar_t,wx containers,compatible with 2.8)
Boost: 1.58.0
KiCad - Compiler: GCC 5.4.0 with C++ ABI 1009

description: updated
Maciej Suminski (orsonmmz) wrote :

Hi Sergey,

Nice catch. I think the basic thing we should do is to add a sanity check to assure that every pin has only one net assigned, otherwise display an error. I am not sure if there is another way to short two nets, but it would be a simple precaution in case we have not anticipated other problems.

In my opinion designers should avoid implicit connections using a common pin of a multi-unit device. It makes schematics harder to read than necessary, but I do not want to tell users how to draw wires. It means I do not have any strong opinion about the net assignment resolution, I would just put in place means to detect anomalies.

Sergey A. Borshch (sb-sf) wrote :

Hi Maciej.

It was just an example, as simple as possible, to show the bug. In my real project MCU has many functions on almost any pin and I grouped them into gates (example: gate A is all pins as GPIO, gate C is all pins that USART1 can be connected to, gate H is all pins of SPI1 etc.). One pin used in schematics as USART1 TX almost always remains unconnected in GPIO and other gates. Netlist generator automatically assigns net to that unconnected pin in GPIO gate and assigns other (automatic or named) net to (the same) connected pin. And this second, desired net gets discarded at netlist loading because non-existing automatic net assigned to not connected pin instance get precedence over existing net. I think all unnamed nets connected to the same pin instance should get the same automatic net name or name of named net if at least one net connected to pin is named (as it was in kicad two or more years ago), or rise error message at ERC and netlist generation if instances of same pin are connected to more than one named net.

 By the way PCAD automatically adds global label to common pin if pin is already connected in other gate.

Jeff Young (jeyjey) on 2018-04-06
summary: - netlist generated incorrectly
+ netlist generated incorrectly for shared pins (cf: multi-gate
+ components)
Jon Evans (craftyjon) on 2018-06-06
Changed in kicad:
assignee: nobody → Jon Evans (craftyjon)
Jeff Young (jeyjey) on 2018-07-27
Changed in kicad:
status: New → Confirmed
importance: Undecided → Medium
Sergey A. Borshch (sb-sf) wrote :

Still buggy with new algorithm in version 5.1.0-114-ge7900e9. Again any instance of same pin gets its own net name and only first net loaded from netlist.

Jon Evans (craftyjon) wrote :

Thanks for the update Sergey, I will test this soon.

Jon Evans (craftyjon) on 2019-04-09
Changed in kicad:
milestone: none → 6.0.0-rc1
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