Comment 9 for bug 1571930

Hi,

On 10.07.2016 11:52, Novak Tamas wrote:

> Decoupler capacitor case may not be regarded as a distance constraint.

The answer is somewhere in the middle. It would be nice to have distance
and loop area constraints, but I won't touch that until net ties are done.

JP has identified the main problem with net ties though -- we don't know
how the layouter wants to do the connections. With the "net ties as
ratsnest anchors" approach I favour, this should be doable:

1. via - trace - capacitor - trace - ic

Place the net tie on the capacitor pad.

2. via in capacitor pad - trace - ic

Place the net tie either on the via or on the capacitor pad.

3. capacitor - trace - via - trace - ic

Place the net tie on the via.

4. capacitor - trace - via in ic pad

Place the net tie either on the via or on the ic pad.

With Altium style net ties, that doesn't work.

I've been writing a lengthy document about this, I'm just waiting for
the official developer wiki to open so I can publish it.

> If a "this pin is part of net1, while also the member of net2" function was implemented (this info must be registered somehow both in .sch and netlist), it worked like this:

Checking against known use cases:

1. analog/digital ground: doesn't work, no pins involved
2. shunt resistors: solved nicely
3. decoupling caps: unclear whether we win much here
4. length matching: doesn't work, pins on the wrong side

> In case of decouplers,
> 1 - make a connection between C (capacitor pin) and P (one Vdd pin of the package): net1
> 2 - select C pin, and click the new "net tie" tool
> 3 - select the net connecting to (net2). Only from a list of named nets (no "Net-(P3-Pad2)" kinda names interested) like PWR_GND, +3.3V etc. Selecting graphically (the whole net highlite while hovering over) would be nice, but not necessary.

How would you represent that in the schematic? Keep in mind that
anything that goes into the netlist needs to be obvious when you look at
the schematic.

   Simon