Comment 8 for bug 1571930

Hi,

On 09.07.2016 08:18, jean-pierre charras wrote:

> I maintain Net ties and decoupling capacitors are very different cases:

I agree -- decoupling capacitors cannot be fully solved with net ties.

The main difficulty I have in the layout of the capacitors is not
distance, but knowing which capacitor belongs to which pin. If I place a
net tie between the power rail on one side, and the capacitor and the IC
pin on the other, the ratsnest line will connect each pin to its
capacitor, which would be a marked improvement.

> They need only a constraint: max distance between they pin x and the pin y of the component to decouple (which is not always a power net).
> This is the only one constraint you have for decoupling capacitors, from the point of view of board design.

Yes, length and loop area constraints would be really great to have as
well, and we could also translate these into a usable ratsnest (length
constrained connections will always be drawn, even if another ratsnest
line would be shorter).

I think I can set up a blueprint for that as well once the wiki goes live,

   Simon