Comment 5 for bug 1571930

Hi,

On 08.07.2016 20:28, jean-pierre charras wrote:

> For me net ties and decoupling capacitors are two different and unrelated things.
> Both are important, but are different features.

Indeed. The schematic would probably not use a "net tie" tool for that,
because it doesn't enhance readability at all, and it would be a lot of
work to create the schematic.

In the board layout however, the functionality required for decoupling
capacitors and for net ties is so similar that it makes sense to treat
them the same.

> * Net ties are related to netlist management.
> * Decoupling capacitors are related to routing constraints management.
> This is very different.

Net ties are a mixture of both -- technically, digital and analog ground
are connected by copper, so you could argue that they're the same net,
and the only difference between them is a routing constraint.

> I am not sure decoupling capacitors constraints must be fixed at
> schematic level (at least from the point of view of efficiency),
> although fixing these constraints at schematic level has an interest: it
> open the door to an automatic placement of decoupling capacitors.

I think that it would be nice to have a "table" schematic element for
things like this -- the table would be printed on the sheet it is placed
on as text, and netlist items can be created from it. This could also be
used for the power supply pins on logic gates -- the table would list
the hidden pins and the nets they are connected to.

> On the other hand, fixing these constraints at schematic level could
> creates a lot more work than just made a good layout by a skilled
> designer, without ensure there is no error.

I'm certainly not a skilled designer, so I try to add functions to help
me catch errors early.

   Simon