Comment 19 for bug 1571930

As a quick comment, one more use case (which has been implied but not mentioned explicitly in this thread) is net ties on inner layers, which is quite a big deal for mixed-signal design. See https://electronics.stackexchange.com/questions/471567/kicad-net-tie-on-inner-layer for my current use case.

Also, if this is coming as a full feature only in 6.0, it would be very nice to have some kind of a workaround/hack before that which doesn't give persistent errors (so the hack mentioned in https://forum.kicad.info/t/footprints-pads-on-internal-layers/11214/21 doesn't quite work, though just removing the error messages and making the inner pads visible might be enough to make this tolerable, as mentioned in the thread).

For my specific use case, a possible nice first class implementation could be that the net tie would actually appear as a special zone in pcbnew (obviously also somehow visible in eeschema), which would be allowed to connect to two different zones (and would then generate the corresponding short in the netlist too). This would allow drawing the connection on the PCB in whichever shape appears most useful once the routing gets underway. Unfortunately I don't have the time to analyze right now how this would affect the other use cases mentioned in this thread.