Comment 15 for bug 1571930

On 7/27/2016 6:14 PM, Evan Shultz wrote:
> @Novak Tamas If only a label is used to indicate a net tie, what is the
> physical implementation? How does the designer specify the location on
> the PCB where the nets are joined? While there may be a good solution
> that is abstract, like a table or property, I wonder if an actual
> component is better simply because of legacy/continuity with other
> software so users will already know what to do with less
> documentation/explanation?
>
> To educate myself I installed eval versions of the big, commercial ECAD
> tools to see what they do regarding net ties. Along with searching
> online and reading the help files, I made a minimal design to show the
> net tie feature; it's entirely possible that I didn't find the
> correct/best way to perform net ties in the various tools so please
> share if you have thoughts.
>
> My criteria for success is the fundamental requirement of a net tie:
> join 2 or more nets at a specific point on the PCB, without creating
> intrinsic DRC errors, and with a "correct" netlist file. I've used a
> multi-pin component which had a non-Cu line that was Gerber'd out to the
> appropriate copper layer. A place keepout and route keepout was located
> between the pins so that the user couldn't create an unexpected short
> with the copper that would appear in the physical board. This worked,
> but there were always issues with the part not being used properly and
> the netlist not showing the net shorts which needed to be manually
> mentioned to the fab house. It was a big pain. I believe this type of
> implementation is possible in every PCB design tool, but since it's
> generally prone to broken manufacturing outputs or generates unavoidable
> DRC errors I'm not considering it as a solution.
>
> Below you'll find a more detailed explanation of what I found in each
> tool, but here's the summary: to me Allegro is the winner as it's easy
> and flexible. It doesn't require a schematic implementation, but
> supports it if desired. Zuken and Altium are pretty close in designing
> with the net tie, but get demerits by not showing the short in an
> IPC-356 netlist. PADS is loses because even though it handles the
> netlist issue nicely it's limited in how, and how easily, the board can
> be designed.
>
> Cadence Allegro PCB Designer (DE-CIS or DE-HDL + Allegro 16.6-2015)
> Allegro supports a special net_short property on a schematic or PCB pin which allows those nets to be shorted at the pin. The property syntax is "net_short = <net1>:<net2>:<net3>...". A DRC error will be created a for net short during routing, even during routing the trace to the pin, but after placing the trace the error will be supposed. Zones can be used in place of traces. The route must start at the first net in the net_short sequence and go to the later nets (routing it backwards will leave the DRC error). Because there need not be a schematic component, if the nets are changed in the schematic the property must be updated in the board; conversely, a schematic component can be created with the property already added for common net shorts, like between AGND and DGND. Generating an IPC-356 netlist has a special section where net shorts are shown. Here's an overly complicated explanation using the CIS front-end (it can be done solely on the board and is simpler than it looks):
> https://community.cadence.com/CSSharedFiles/forums/storage/27/62487/Net_Short_Defintion.pdf
> http://www.daltools.com/doc/NetShort/NetShort.pdf
>
> Zuken CADSTAR Express 17.0
> A special schematic "Starpoint" symbol is placed on the schematic which allows signals to be routed to either end of this multi-pin device. When placed on the PCB, it's a 1-pin device with multiple ratsnest coming out of it. The IPC-356 netlist, however, appears to show all nets as discrete instead of indicating the shorts.
>
> Altium Designer 16.1
> Altium has special "Net Tie" and "Net Tie (in BOM)" types for components. The footprint allows routing different nets to the pins but prevents net short DRC errors with the footprint's copper, allowing different nets to be joined as long as those nets are only connected by the copper in the footprint (not by directly routing the nets together). The shorting copper can be part of the footprint or can be added by the designer. Again, nets that are tied together are shown as unique nets in an IPC-356 netlist.
> http://altiumpcbdesigner.blogspot.com/2012/05/net-ties-how-to.html
> http://www.smtnet.com/library/files/upload/NetTies-and-How-to-Use-Them.pdf (linked from above)
> http://altiumpcbdesigner.blogspot.com/2015/07/short-circuit-rules.html
>
> PADS VX1.2 Standard (xDX Designer + PADS Layout)
> PADS allows a copper zone to be set as a "bridge", which can connect vias, trace, pads, etc. from multiple nets. The zone must be of a "copper" type, and not an intelligent "copper pour" type. Routing copper or placing pads from a different net into the zone does not automatically add clearance but instead generates a DRC error which must be corrected manually. An IPC-356A netlist shows a new net which is clearly marked as a bridge between the two discrete nets in the design. Interestingly, while this feature was implemented sometime before 2011, in 2014 there is another thread where users are complaining about not being able to tie nets together; whether this is user error or not I cannot say.
> https://communities.mentor.com/thread/6914
> https://communities.mentor.com/thread/2091
>

@Evan, thank you for taking the time and effort to create this
evaluation. It saves everyone involved in the discussion the time of
doing it themselves. There is a lot of useful information here. I like
the way Allegro handles net ties but I think Altium does a nicer job of
providing a clear method for editing the net tie information.