Nick Østergaard (nickoe): My current version info is that pcbnew claims (2016-03-29 BZR 6653), and that matches the comment in the top of the .kicad_pcb file. However, I did recently update source, and the PCB file itself may have been generated initially from a copy around mid-February.
If it's any help, the settings my .kicad_pcb file are:
Nick Østergaard (nickoe): My current version info is that pcbnew claims (2016-03-29 BZR 6653), and that matches the comment in the top of the .kicad_pcb file. However, I did recently update source, and the PCB file itself may have been generated initially from a copy around mid-February.
If it's any help, the settings my .kicad_pcb file are:
(kicad_pcb (version 4) (host pcbnew "(2016-03-29 BZR 6653)-product")
(general
(links 29)
(no_connects 1)
(area 101.006729 63.02641 147.913272 87.13192)
(thickness 1.6)
(drawings 20)
(tracks 83)
(zones 0)
(modules 11)
(nets 14)
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup trace_width 0.2032) clearance 0.2032) to_mask_ clearance 0.2) axis_origin 0 0) elements FFFFEF7F) layerselection 0x010f0_ffffffff) usegerberextens ions true) excludeedgelaye r true) hpglpennumber 1) hpglpendiameter 15) plotreference true) plotinvisiblete xt false) subtractmaskfro msilk false) scaleselection 1) outputdirectory ""))
(last_
(trace_
(zone_clearance 0.3048)
(zone_45_only no)
(trace_min 0.2)
(segment_width 0.2)
(edge_width 0.15)
(via_size 0.508)
(via_drill 0.4064)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0)
(uvia_min_drill 0)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 0.762 0.762)
(mod_text_width 0.127)
(pad_size 1.2 0.75)
(pad_drill 0)
(pad_
(aux_
(visible_
(pcbplotparams
(
(
(
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(
(hpglpenspeed 20)
(
(psnegative false)
(psa4output false)
(
(plotvalue true)
(
(padsonsilk false)
(
(outputformat 1)
(mirror false)
(drillshape 0)
(
(
)