pcb

Wish list

Bug #699559 reported by gordonstalker
6
This bug affects 1 person
Affects Status Importance Assigned to Milestone
pcb
Invalid
Wishlist
Bert Timmerman

Bug Description

I don't want to sound like I am complaining, but I think
PCB could do with a lot of enhancements.

As a pcb design proffessional, I would be very happy to
see a highly featured, and easy to use circuit layout
tool, comparable to the best 'proffesional' offerings,
which are very expensive. (And some of them are very
poor!)

If such a tool were available it would (I think) go a long
way towards stimulating commercial vendors to improve
inter-operability between the different packages.

At this moment in time, each vendor uses their own
proprietary file formats. This means that once you select
a design package, you are more-or-less stuck with that
supplier. It also means that designers cannot take
on 'remedial' work produced using other software, which
is not good for the customers either!

Add to that the way they continually 'upgrade' their
products, so that older versions cannot read files
produced by the latest versions, and you can see the
problem. But you probably know all this.

Unfortunately in it's current state PCB dosen't really
compete. While it is useful for the 'odd' board for hobby
and 'student' use, this is mainly (I think) cos it is free.

I would like to make a few suggestions under the
following headings.

1. 'netlists'

1.1 Component package data.

'Proffessional' netlist files usually contain details of the
packages used in the design so that the layout tool can
automatiacally load the corresponding component. This
need not be particularily sophisticate, simply
associating a 'footprint' name with a part reference would
be sufficient. (At least initially)

It is often convenient to place more component detail in
the netlist such as part names and values, so it would
be nice to include this option in a specifiction for the
netlist, even if it is not supported at first.

This allows the circuit designer to specify packages at
the schematic 'capture' stage of design.

I realise that this also requires the capture/schematic
tool to produce such a file, but I think that this would
happen if the option was there.
I also realise that simulation tools such a spice tend to
place device and connectivity data in separate files, and
that may be a good approach for functional analysis
allowing for libraries of sub-circuits to be constructed.
But that is not an advantage to the circuit designer
where the unit of re-use is the component package.

1.2 Net data.

It is not uncommon for such data as trace width,
clerances and impedance also to be specified for
individual at the schematic stage. The same should
apply here.

2. Design checking.

It should be possible to define design rules for each of
the element types and layers. For example it should
possible to turn off design checking for silk-screen
layers.

2.1 Global Clearances.

Global clearances should be specified seperately for the
following type of feature.

Signal traces, Power traces, Surface mount pads, thru-
hole pads, Vias, Silk-screen to pad, board-edges,drills,
copper pours.

These should be specified as clearances between type-
pairs.

2.2 Individual net clearances

This is a more advanced feature. Clearances should be
specifiable on a net-by-net basis, overriding global
settings. This is useful for mixed technology and voltage
designs.

A lot of 'proffessional' software overlooks this. On more
than one occasion I have been faced with a design with
high voltage nets requiring clearances (and creepages!)
of sevaral millimetres, on the same board as surface
mount devices with pin pitches of 0.5mm. The package
used did not support this feature, and it took several full
working days to check the board clerances!

3. Board outlines.

Although many pcb's have a rectilinear outline, this is
not always the case. Even when the are many are not in
the form of a single rectangle. Cut-out areas are also
often required.

In summary.....

The above represents a wish-list of the things I would
like to see in a PCB layout program. The list is by no
means exhaustive, there are 'look and feel' issues which
probably need to be addressed, and such like, but I
think that the above is enough to be going on with.

Gordon Stalker

Revision history for this message
Bert Timmerman (bert-timmerman) wrote :

Hi Gordon,

I have a couple of comments on your wishlist:

It would help if you gave the subject a meaningful name, i.e. not "wishlist" as most features requested could be considered whishes :-)

It would help if you break down your wishlist into single items and file those as separate feature requests.
In this way you have a better chance of getting one or more wishes granted.

1.1
Can already be done by attaching the "footprint=" attribute in gschem and running gsch2pcb.

3.
Can be done with a layer called "outline" (= special layer name).

Kind regards,

Bert Timmerman.

Revision history for this message
Bert Timmerman (bert-timmerman) wrote :

This collection of bug reports affects both gEDA and pcb.
I will try to spilt this one "wishlist" up into separate bug reports with meaningfull names and check for duplicates.
After this exercise this original "wishlist" bug report should be set to "Won't Fix".

Changed in pcb:
assignee: nobody → Bert Timmerman (bert-timmerman)
status: New → In Progress
Revision history for this message
Peter Clifton (pcjc2) wrote :

Bert, for this one, "Invalid" might be a useful status when you're done.

Revision history for this message
Bert Timmerman (bert-timmerman) wrote :

Close out report.

Wishlist item #1.1 Component package data.
As already stated this can be resolved by attaching the "footprint=" attribute in gschem and running gsch2pcb or using "Import schematic" within pcb.

Wishlist item #1.2 Net data.
Split into:
a) Trace width and clearances are superseded in (pcb and gEDA) bug report #698771 "add route style attributes".
b) Required impedance (specified in netlist) for a net/track to be automagically implemented into a pcb routing style --> separate bug report #700400.

Wishlist item #2. Design checking.
--> separate bug report #700408.

Wishlist item #2.1 Global Clearances.
--> separate bug report #700414.

Wishlist item #2.2 Individual net clearances.
--> separate bug report #701608.

Wishlist item #3. Board outlines.
--> separate bug report #701621.

Changed in pcb:
status: In Progress → Invalid
Revision history for this message
Peter Clifton (pcjc2) wrote :

Bert, if you use syntax like this, the reports will be linked:

Wishlist item #2. Design checking.
--> separate bug #700408.

Wishlist item #2.1 Global Clearances.
--> separate bug #700414.

Wishlist item #2.2 Individual net clearances.
--> separate bug #701608.

Wishlist item #3. Board outlines.
--> separate bug #701621.

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