Comment 166 for bug 541511

(I don't own an 855 and my 845 machine is not available right now, so this is just wild speculation.)

Could some of the chipset buffers be indexed by the SDRAM bank number (and maybe even the row (side) number)? I'm imagining a scenario where the CPU and the GTT sides have separate SDRAM write buffers that are not kept coherent (their access to the actual RAM can be arbitrated), and each write buffer has one or two cache lines for each bank; this might be a relatively easy way to make simultaneous access to different banks in parallel. There seems to be 4 banks on the 845, and the bank number can be between bits 11-12 and 14-15, depending on the DRAM modules installed; perhaps the situation is similar on the 855 as well. If this is the case, 16 physically contiguous pages should cover all banks, while non-contiguous ones might not be so if we are particularly unlucky in intel_i830_setup_flush(), which is called when resuming.

To test this theory, maybe we can print the physical addresses (those within the System RAM range in /proc/iomem) of the allocated i8xx_pages. Then, when we see retried or even failed flushes, perhaps some patterns can be observed.