Comment 0 for bug 2055241

[ Impact ]

* This models on-chip oscillator clock nodes in KV/KR/KD board device trees built for Xilinx products to be in sync with the corresponding board schematic
* Currently a few clocks were not modelled which are planned to be included now.
* Most clocks in board device trees are currently included so this should have minimal size impact.
* The correct and cleanest approach is to model clock sources in Xilinx's application dtsi's in order to reference these clock nodes from the board device tree rather than having duplicated nodes in application overlay dtbo's

[ Test Plan ]

* Xilinx will verify they can load the dtbo's for the FPGA during runtime

[ Where problems could occur ]

* There could be an unexpected impact since there are discrepancies between some revA vs revB board device trees, all clock nodes not being modelled to be in sync with board schematics

[ Other Info ]

https://github.com/Xilinx/linux-xlnx/commit/bd1a7261325afa7526ed12fbaeb8f2e939bd02f8
https://github.com/Xilinx/linux-xlnx/commit/d9d492b32494611dbcc422d9f365a59df20c69b1
https://github.com/Xilinx/linux-xlnx/commit/a0fe3083d290f8507922a68daa60cb92d76d56b2