I guess you mean "there is only one PPL in the CPU, all cores get the resulting clock". This would mean the readout of i7z in the idle case, where each core has a different multiplier and a different clock, is fake.
I guess you mean "there is only one PPL in the CPU, all cores get the resulting clock". This would mean the readout of i7z in the idle case, where each core has a different multiplier and a different clock, is fake.