Comment 65 for bug 946311

I was able to reduce count of patches to this range:
dfc9ef2 drm/i915: set ring->size in common ring setup code
6a848cc drm/i915: rip out ring->irq_mask
1500f7e drm/i915: hide (seqno-1) in ringbuffer code
e3a5a22 drm/i915: fix for when semaphore updates fail
5816d64 drm/i915: i915_gem_object_sync must handle NULL
f82cfb6 drm/i915: allow PCH PWM override on IVB
b6834bd drm/i915: disable turbo on ValleyView for now
bfa3384 drm/i915: check PPS regs for sanity when using eDP
f817586 drm/i915: re-init modeset hw state after gpu reset
f841319 drm/i915: Allow concurrent read access between CPU and GPU domain
211c568 drm/i915: simplify ppgtt setup
e3aef17 drm/i915: make DP configuration vars less confusing in ironlake_crtc_mod
0136db5 drm/i915: rc6 in sysfs
d1686ae drm/i915: Ironlake shares the same video sprite controls as Sandybridge
e2ba4fb drm/i915/intel_i2c: remove POSTING_READ() from gmbus transfers
90e6b26 drm/i915/intel_i2c: reuse GMBUS2 value read in polling loop
56f9eac drm/i915/intel_i2c: use INDEX cycles for i2c read transactions
72d66af drm/i915/intel_i2c: use WAIT cycle, not STOP
e646d57 drm/i915/intel_i2c: always wait for IDLE before clearing NAK
7a39a9d drm/i915/intel_i2c: use double-buffered writes
26883c3 drm/i915/intel_i2c: handle zero-length writes
3fdcf43 drm/i915: use register name when disabling VGA
2911a35 drm/i915: use semaphores for the display plane
9a5a53b drm/i915: Reorganise rules for get_fence/put_fence

Most of them like minefield. Some where before e3aef17 i get just black screen, and some where after it i get oops.