This patch would confirm my hypothesis that is an invalid unfenced alignment:
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index f136899..c970b81 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1416,6 +1416,7 @@ i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_ob obj->tiling_mode == I915_TILING_NONE) return 4096;
+ return i915_gem_get_gtt_size(obj); /* * Older chips need unfenced tiled buffers to be aligned to the left * edge of an even tile row (where tile rows are counted as if the bo is
This patch would confirm my hypothesis that is an invalid unfenced alignment:
diff --git a/drivers/ gpu/drm/ i915/i915_ gem.c b/drivers/ gpu/drm/ i915/i915_ gem.c gpu/drm/ i915/i915_ gem.c gpu/drm/ i915/i915_ gem.c get_unfenced_ gtt_alignment( struct drm_i915_gem_ob
obj- >tiling_ mode == I915_TILING_NONE)
return 4096;
index f136899..c970b81 100644
--- a/drivers/
+++ b/drivers/
@@ -1416,6 +1416,7 @@ i915_gem_
+ return i915_gem_ get_gtt_ size(obj) ;
/*
* Older chips need unfenced tiled buffers to be aligned to the left
* edge of an even tile row (where tile rows are counted as if the bo is