Comment 209 for bug 1098334

Revision history for this message
In , Chris Wilson (ickle) wrote :

Nevertheless it was a good catch.

commit 1cbc59a917e7352fc68aa0e26b1575cbd0ceab0d
Author: Edward Sheldrake <email address hidden>
Date: Mon Feb 3 09:34:33 2014 +0000

    sna/gen4,5: Fix setting pipe control cache flush bits

    Cache flush bits are on dword 0, not 1, on gen4 and gen5. Also texture
    cache invalidate is only available from Cantiga onwards.