Comment 207 for bug 1098334

Running with all workarounds disabled, this change doesn't fix anything nor seem to make any difference, but anyway:
Shouldn't the cache flush bits be in dword 0 for gen4 GEN4_PIPE_CONTROL? Maybe gen5 also?

diff --git a/src/sna/gen4_render.c b/src/sna/gen4_render.c
index 1d164b6..894418b 100644
--- a/src/sna/gen4_render.c
+++ b/src/sna/gen4_render.c
@@ -575,8 +575,10 @@ inline static void
 gen4_emit_pipe_flush(struct sna *sna)
 {
 #if 1
- OUT_BATCH(GEN4_PIPE_CONTROL | (4 - 2));
- OUT_BATCH(GEN4_PIPE_CONTROL_WC_FLUSH);
+ OUT_BATCH(GEN4_PIPE_CONTROL |
+ GEN4_PIPE_CONTROL_WC_FLUSH |
+ (4 - 2));
+ OUT_BATCH(0);
  OUT_BATCH(0);
  OUT_BATCH(0);
 #else
@@ -601,8 +603,10 @@ inline static void
 gen4_emit_pipe_invalidate(struct sna *sna)
 {
 #if 0
- OUT_BATCH(GEN4_PIPE_CONTROL | (4 - 2));
- OUT_BATCH(GEN4_PIPE_CONTROL_WC_FLUSH | GEN4_PIPE_CONTROL_TC_FLUSH);
+ OUT_BATCH(GEN4_PIPE_CONTROL |
+ GEN4_PIPE_CONTROL_WC_FLUSH | GEN4_PIPE_CONTROL_TC_FLUSH |
+ (4 - 2));
+ OUT_BATCH(0);
  OUT_BATCH(0);
  OUT_BATCH(0);
 #else