@@ -2776,6 +2787,7 @@ gen4_render_fill_op_done(struct sna *sna, const struct sna_fill_op *op)
if (sna->render.vertex_offset)
gen4_vertex_flush(sna);
kgem_bo_destroy(&sna->kgem, op->base.src.bo);
+ gen4_emit_pipe_invalidate(sna);
}
static bool
I've also tried setting "Render Cache Operational Flush Enable" of the Cache_Mode_0 register with intel_reg_write, this made no difference.
I was also wondering if firefox is particularly bad because it uses it's own old version of cairo which seems to be version 1.9.8 plus lots of patches.
I am wondering if some extra flushes are needed in regard to what the G45 PRM PDFs say about the BLT (section 8.6, vol 1b p. 170)
git + this gives only a moderate amount of corrupt rendering: gen4_render. c b/src/sna/ gen4_render. c gen4_render. c gen4_render. c
diff --git a/src/sna/
index e239c21..f150e5b 100644
--- a/src/sna/
+++ b/src/sna/
@@ -63,7 +63,7 @@
#define NO_FILL_BOXES 0
#define NO_VIDEO 0
-#define MAX_FLUSH_VERTICES 1 /* was 6, https:/ /bugs.freedeskt op.org/ show_bug. cgi?id= 55500 */ /bugs.freedeskt op.org/ show_bug. cgi?id= 55500 */
+#define MAX_FLUSH_VERTICES 12 /* was 6, https:/
#define GEN4_GRF_ BLOCKS( nreg) ((nreg + 15) / 16 - 1)
@@ -571,26 +571,28 @@ static void gen4_emit_ vertex_ buffer( struct sna *sna, pipe_flush( struct sna *sna) GEN4_PIPE_ CONTROL | (4 - 2)); GEN4_PIPE_ CONTROL_ WC_FLUSH) ; GEN4_PIPE_ CONTROL_ WC_FLUSH | GEN4_PIPE_ CONTROL_ TC_FLUSH) ; MI_FLUSH | MI_INHIBIT_ RENDER_ CACHE_FLUSH) ;
inline static void
gen4_emit_
{
-#if 1
+#if 0
OUT_BATCH(
- OUT_BATCH(
+ OUT_BATCH(
OUT_BATCH(0);
OUT_BATCH(0);
#else
OUT_BATCH(
+ /* OUT_BATCH(MI_NOOP); */
#endif
}
inline static void pipe_break( struct sna *sna) GEN4_PIPE_ CONTROL | (4 - 2)); GEN4_PIPE_ CONTROL_ TC_FLUSH) ; MI_FLUSH | MI_INHIBIT_ RENDER_ CACHE_FLUSH) ;
gen4_emit_
{
-#if 1
+#if 0
OUT_BATCH(
- OUT_BATCH(0);
+ OUT_BATCH(
OUT_BATCH(0);
OUT_BATCH(0);
#else
OUT_BATCH(
+ /* OUT_BATCH(MI_NOOP); */
#endif
}
@@ -599,11 +601,12 @@ gen4_emit_ pipe_invalidate (struct sna *sna) GEN4_PIPE_ CONTROL | (4 - 2)); GEN4_PIPE_ CONTROL_ WC_FLUSH | GEN4_PIPE_ CONTROL_ TC_FLUSH) ; GEN4_PIPE_ CONTROL_ WC_FLUSH | GEN4_PIPE_ CONTROL_ TC_FLUSH | GEN4_PIPE_ CONTROL_ IS_FLUSH) ; MI_FLUSH) ; MI_FLUSH) ; /* | MI_STATE_ INSTRUCTION_ CACHE_FLUSH */
{
#if 0
OUT_BATCH(
- OUT_BATCH(
+ OUT_BATCH(
OUT_BATCH(0);
OUT_BATCH(0);
#else
- OUT_BATCH(
+ OUT_BATCH(
+ /* OUT_BATCH(MI_NOOP); */
#endif
}
@@ -781,7 +784,10 @@ gen4_emit_ urb(struct sna *sna)
urb_cl_end = urb_gs_end + URB_CL_ENTRIES * URB_CL_ENTRY_SIZE;
urb_sf_end = urb_cl_end + URB_SF_ENTRIES * URB_SF_ENTRY_SIZE;
urb_cs_end = urb_sf_end + URB_CS_ENTRIES * URB_CS_ENTRY_SIZE;
- assert(urb_cs_end <= 256);
+ if (sna->kgem.gen >= 045)
+ assert(urb_cs_end <= 384);
+ else
+ assert(urb_cs_end <= 256);
while ((sna->kgem.nbatch & 15) > 12) BATCH(MI_ NOOP); composite_ done(struct sna *sna, bo_destroy( &sna->kgem, op->src.bo);
OUT_
@@ -1623,6 +1629,7 @@ gen4_render_
kgem_
sna_render_ composite_ redirect_ done(sna, op); pipe_invalidate (sna);
+ gen4_emit_
}
static bool composite_ spans_done( struct sna *sna,
@@ -2154,6 +2161,7 @@ gen4_render_
kgem_ bo_destroy( &sna->kgem, op->base.src.bo); composite_ redirect_ done(sna, &op->base); pipe_invalidate (sna);
sna_render_
+ gen4_emit_
}
static bool vertex_ flush(sna) ; composite_ redirect_ done(sna, &tmp); bo_destroy( &sna->kgem, tmp.src.bo); pipe_invalidate (sna);
@@ -2500,6 +2508,7 @@ fallback_blt:
gen4_
sna_render_
kgem_
+ gen4_emit_
return true;
fallback_ tiled_dst: copy_done( struct sna *sna, const struct sna_copy_op *op) vertex_ offset) vertex_ flush(sna) ; pipe_invalidate (sna);
@@ -2535,6 +2544,7 @@ gen4_render_
{
if (sna->render.
gen4_
+ gen4_emit_
}
static bool fill_boxes( struct sna *sna,
@@ -2736,6 +2746,7 @@ gen4_render_
gen4_ vertex_ flush(sna) ; bo_destroy( &sna->kgem, tmp.src.bo); pipe_invalidate (sna);
kgem_
+ gen4_emit_
return true;
}
@@ -2776,6 +2787,7 @@ gen4_render_ fill_op_ done(struct sna *sna, const struct sna_fill_op *op) vertex_ offset) vertex_ flush(sna) ; bo_destroy( &sna->kgem, op->base.src.bo); pipe_invalidate (sna);
if (sna->render.
gen4_
kgem_
+ gen4_emit_
}
static bool
I've also tried setting "Render Cache Operational Flush Enable" of the Cache_Mode_0 register with intel_reg_write, this made no difference.
I was also wondering if firefox is particularly bad because it uses it's own old version of cairo which seems to be version 1.9.8 plus lots of patches.