Comment 12 for bug 554637

(In reply to comment #11)
>
> How does any of that (some of which I'll have to google to understand fully)
> account for different behaviour with exactly the same modeline with exactly the
> same hardware? Surely the same line should produce the same timing?
>

Changes to the pll divider selection algorithm could account for the change. Basically you have a reference clock on the board (say 27 Mhz) and the driver uses a set of dividers to derive the requested pixel clock. Sometimes there are multiple sets of dividers that match the requested frequency. Other times there is not an exact match and the driver has to get as close as possible. These variances can affect the timing sent to your monitor. For example, in the case of your modeline, the driver isn't able to find an exact match:

ref_freq: 2700
freq: 179260000
best_freq: 175000000
best_feedback_div: 350
best_ref_div: 27
best_post_div: 2

dot clock = (ref_freq * (feedback_div / ref_div)) / post_div;