Comment 81 for bug 291040

(In reply to comment #71)
> (In reply to comment #69)
> > Created an attachment (id=28899) [details] [details]
> > patch for pre-r6xx chips
> >
> > This seems to fix the DFS issues for me on my problematic r5xx card. Basically
> > for small xfers we do the blit twice to make sure it's hit memory.
>
> Hmm I don't like the idea. Surely there must be some way to correctly determine
> the blit has really completed?
> Otherwise, isn't actually the size (so something like width * height * bpp)
> rather than width or height relevant for this?
>

Yes, the size is relevant. There's apparently some threshold for the write combiner in the bus interface.