(In reply to comment #45)
> (In reply to comment #44)
> > I'm attaching the patch, hopefully this would help track down the issue.
>
> Interesting; I think this could indicate that
> radeon_do_wait_for_idle()/radeon_do_pixcache_flush() in the DRM are missing
> something for properly waiting for the cache flush to be finished.
Is it possible that cache is idle but memory controller not yet (that is would need to wait for MC_IDLE)? Or another idea, is writing DSTCACHE_CTLSTAT for flushing cache and immediately reading it back guaranteed to give the right answer (busy if there's something to flush) or is there some delay needed?
(In reply to comment #45) do_wait_ for_idle( )/radeon_ do_pixcache_ flush() in the DRM are missing
> (In reply to comment #44)
> > I'm attaching the patch, hopefully this would help track down the issue.
>
> Interesting; I think this could indicate that
> radeon_
> something for properly waiting for the cache flush to be finished.
Is it possible that cache is idle but memory controller not yet (that is would need to wait for MC_IDLE)? Or another idea, is writing DSTCACHE_CTLSTAT for flushing cache and immediately reading it back guaranteed to give the right answer (busy if there's something to flush) or is there some delay needed?