I think vsync is calculated wrong when an interlaced modeline is read, since xrandr sets it correctly. Anything i can do to help you?
> As to pre-avivo chips, > unfortunately, I cannot reproduce any problems with with interlaced modes here.
I think vsync is calculated wrong when an interlaced modeline is read, since xrandr sets it correctly. Anything i can do to help you?
> As to pre-avivo chips,
> unfortunately, I cannot reproduce any problems with with interlaced modes here.