basically to benefit from apicv, we need clear MSR bitmap for
corresponding x2apic MSRs:
0x800 - 0x8ff: no read intercept for apicv register virtualization
TPR,EOI,SELF-IPI: no write intercept for virtual interrupt
delivery
Virtual interrupt delivery avoids Xen to inject vAPIC interrupts
manually, which is fully taken care of by the hardware. This needs
some special awareness into existing interrupr injection path:
For pending interrupt from vLAPIC, instead of direct injection, we may
need update architecture specific indicators before resuming to guest.
Before returning to guest, RVI should be updated if any pending IRRs
EOI exit bitmap controls whether an EOI write should cause VM-Exit. If
set, a trap-like induced EOI VM-Exit is triggered. The approach here
is to manipulate EOI exit bitmap based on value of TMR. Level
triggered irq requires a hook in vLAPIC EOI write, so that vIOAPIC EOI
is triggered and emulated
Signed-off-by: Gang Wei <email address hidden>
Signed-off-by: Yang Zhang <email address hidden>
Signed-off-by: Jiongxi Li <email address hidden>
Committed-by: Keir Fraser <email address hidden>
There are 3 commits for this feature:
1. 487613a95c1bf64 41e8b15e43
commit c892426ce32dc68
Author: Jiongxi Li <email address hidden>
Date: Mon Sep 17 21:06:02 2012 +0100
xen: add virtual x2apic support for apicv
basically to benefit from apicv, we need clear MSR bitmap for EOI,SELF- IPI: no write intercept for virtual interrupt
corresponding x2apic MSRs:
0x800 - 0x8ff: no read intercept for apicv register virtualization
TPR,
delivery
Signed-off-by: Jiongxi Li <email address hidden>
Committed-by: Keir Fraser <email address hidden>
2. bd4c8c56e9d3d76 801d061842
commit 25b81a7941d71fa
Author: Jiongxi Li <email address hidden>
Date: Mon Sep 17 21:05:11 2012 +0100
xen: enable Virtual-interrupt delivery
Virtual interrupt delivery avoids Xen to inject vAPIC interrupts
manually, which is fully taken care of by the hardware. This needs
some special awareness into existing interrupr injection path:
For pending interrupt from vLAPIC, instead of direct injection, we may
need update architecture specific indicators before resuming to guest.
Before returning to guest, RVI should be updated if any pending IRRs
EOI exit bitmap controls whether an EOI write should cause VM-Exit. If
set, a trap-like induced EOI VM-Exit is triggered. The approach here
is to manipulate EOI exit bitmap based on value of TMR. Level
triggered irq requires a hook in vLAPIC EOI write, so that vIOAPIC EOI
is triggered and emulated
Signed-off-by: Gang Wei <email address hidden>
Signed-off-by: Yang Zhang <email address hidden>
Signed-off-by: Jiongxi Li <email address hidden>
Committed-by: Keir Fraser <email address hidden>
3. a2b8397b9bdf1a5 3b541df3f3
commit f62b02e177cd03d
Author: Jiongxi Li <email address hidden>
Date: Mon Sep 17 21:04:08 2012 +0100
xen: enable APIC-Register Virtualization
Add APIC register virtualization support
- APIC read doesn't cause VM-Exit
- APIC write becomes trap-like
Signed-off-by: Gang Wei <email address hidden>
Signed-off-by: Yang Zhang <email address hidden>
Signed-off-by: Jiongxi Li <email address hidden>