Comment 0 for bug 1921754

The EPYC-Rome model is missing the IBRS and SSBD flags due to an oversight

https://lists.gnu.org/archive/html/qemu-devel/2021-02/msg07378.html

They have been added as a EPYC-Rome-v2 in

https://lists.gnu.org/archive/html/qemu-devel/2021-03/msg01020.html

This patch depends on the IBRS and AMD SSBD definitions that were added as part of the EPYC-Milan patch:

https://lists.gnu.org/archive/html/qemu-devel/2021-02/msg03370.html

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 8d599bb5b8..888c3a59e2 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -816,8 +816,12 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
 /* Indirect Branch Prediction Barrier */
 #define CPUID_8000_0008_EBX_IBPB (1U << 12)
+/* Indirect Branch Restricted Speculation */
+#define CPUID_8000_0008_EBX_IBRS (1U << 14)
 /* Single Thread Indirect Branch Predictors */
 #define CPUID_8000_0008_EBX_STIBP (1U << 15)
+/* Speculative Store Bypass Disable */
+#define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24)