x86, amd: Avoid cache aliasing penalties on AMD family 15h
Affects | Status | Importance | Assigned to | Milestone | |
---|---|---|---|---|---|
linux (Ubuntu) |
Fix Released
|
Undecided
|
Tim Gardner | ||
Oneiric |
Fix Released
|
Undecided
|
Tim Gardner | ||
Precise |
Fix Released
|
Undecided
|
Tim Gardner |
Bug Description
This patch provides performance tuning for the "Bulldozer" CPU. With its
shared instruction cache there is a chance of generating an excessive
number of cache cross-invalidates when running specific workloads on the
cores of a compute module.
This excessive amount of cross-invalidations can be observed if cache
lines backed by shared physical memory alias in bits [14:12] of their
virtual addresses, as those bits are used for the index generation.
This patch addresses the issue by clearing all the bits in the [14:12]
slice of the file mapping's virtual address at generation time, thus
forcing those bits the same for all mappings of a single shared library
across processes and, in doing so, avoids instruction cache aliases.
It also adds the command line option "align_
which virtual address alignment can be enabled for 32-bit or 64-bit x86
individually, or both, or be completely disabled.
This change leaves virtual region address allocation on other families
and/or vendors unaffected.
Related branches
CVE References
Changed in linux (Ubuntu Precise): | |
status: | In Progress → Fix Released |
This bug is missing log files that will aid in diagnosing the problem. From a terminal window please run:
apport-collect 862583
and then change the status of the bug to 'Confirmed'.
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This change has been made by an automated script, maintained by the Ubuntu Kernel Team.