Comment 98 for bug 349412

Next random patch, this will need to be applied in conjunction with increasing DSPARB:

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_d
index 1edaa3f..962405b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2844,7 +2844,7 @@ static void pineview_disable_cxsr(struct drm_device *dev)
  * A value of 5us seems to be a good balance; safe for very low end
  * platforms but not overly aggressive on lower latency configs.
  */
-static const int latency_ns = 5000;
+static const int latency_ns = 9000;

 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 {

Karl, as an aside what is your memory configuration? I presume DDR2 (since it is an 945GM). But what speed/latency? Jesse thinks there are some bits in the MCHBAR that can help us, but it will probably need a magic table as well.