Comment 87 for bug 349412

Well at least we succeed in generating enough head room for the FIFO.

[drm:intel_update_watermarks], plane B (pipe 0) clock: 138500
[drm:intel_update_watermarks], plane A (pipe 1) clock: 68940
[drm:i9xx_get_fifo_size], FIFO size - (0x00003f9c) A: 28
[drm:i9xx_get_fifo_size], FIFO size - (0x00003f9c) B: 99
[drm:intel_calculate_wm], FIFO entries required for mode: 21
[drm:intel_calculate_wm], FIFO watermark level: 5
[drm:intel_calculate_wm], FIFO entries required for mode: 43
[drm:intel_calculate_wm], FIFO watermark level: 54
[drm:i9xx_update_wm], FIFO watermarks - A: 5, B: 54
[drm:i9xx_update_wm], Setting FIFO watermarks - A: 5, B: 54, C: 2, SR 1

Hah, I wonder if we are now stressing the hardware too much in the other direction.

Tobias, one last test before we look elsewhere:

I915_WRITE(DSPARB, (50 << 7) | 28); /* give's up on all pretence of elegance */