Comment 74 for bug 349412

The argument centers around:

[drm:intel_update_watermarks], plane B (pipe 0) clock: 138500
[drm:intel_update_watermarks], plane A (pipe 1) clock: 68940
[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
[drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
[drm:intel_calculate_wm], FIFO entries required for mode: 21
[drm:intel_calculate_wm], FIFO watermark level: 5
[drm:intel_calculate_wm], FIFO entries required for mode: 43
[drm:intel_calculate_wm], FIFO watermark level: -14
[drm:i9xx_update_wm], FIFO watermarks - A: 5, B: 1
[drm:i9xx_update_wm], Setting FIFO watermarks - A: 5, B: 1, C: 2, SR 1

What should be noted here is that by simply using the preset fifo sizes of 28, 31 we cannot accommodate the external display which requires 43 entires [43 >> 31].

As this is a 915 we should have 96 entries to play with, but the advice is not to modify the fifo sizes at runtime, so to test the hypothesis we can try setting the DSPARB to give the maximum bandwidth to external displays at init:

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 9ddb7b5..edaae6c 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1434,6 +1434,13 @@ static int i915_load_modeset_init(struct drm_device *dev,

        I915_WRITE(INSTPM, (1 << 5) | (1 << 21));

+ /* XXX hack for bug 22996, preset the FIFO to accommodate a 2048 external display */
+ {
+ uint32_t size = I915_READ(DSPARB) & 0x7f;
+ size = (95 - size) << DSPARB_CSTART_SHIFT;
+ I915_WRITE(DSPARB, size);
+ }
+
        ret = intel_fbdev_init(dev);
        if (ret)
                goto cleanup_irq;