Comment 94 for bug 311895
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#94 |
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e3ace39
(Get the code!)
Ah I can believe that VT switches might cause trouble... The diff actually doesn't look too interesting though, mainly LVDS is off. However this part definitely does look weird:
(II) intel(0): FIFO entries - A: 25, B: 0
(II) intel(0): FIFO size - A: 28, B: 59
(WW) intel(0): plane B needs more FIFO entries
That FIFO entries line indicates that pipe B is off. Maybe I don't handle that case correctly...