Comment 12 for bug 1958620

after bisection:

6d7a793aabf31d7ba2b16fc13a94ccf0b90e4be0 is the first bad commit
commit 6d7a793aabf31d7ba2b16fc13a94ccf0b90e4be0
Author: José Roberto de Souza <email address hidden>
Date: Fri May 14 16:22:45 2021 -0700

    drm/i915/display: Allow fastsets when DP_SDP_VSC infoframe do not match with PSR enabled

    When PSR is enabled it handles DP_SDP_VSC, changing revision and all
    the other fields as necessary.
    It can also enabled and disable this SDP as needed without a full
    modeset.

    So here masking DP_SDP_VSC bit when previous and future state PSR
    enabled, it will still be checked when comparing the asked state
    to what was programmed to hardware.

    Cc: Gwan-gyeong Mun <email address hidden>
    Cc: Radhakrishna Sripada <email address hidden>
    Reported-by: Ville Syrjälä <email address hidden>
    Fixes: 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware configuration read out")
    Signed-off-by: José Roberto de Souza <email address hidden>
    Reviewed-by: Gwan-gyeong Mun <email address hidden>
    Link: https://patchwork<email address hidden>

 drivers/gpu/drm/i915/display/intel_display.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)