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1b1ed1a
(Get the code!)
Hi,
WW38.2'21: Confirmed Intel LAN issue; promoted to LAN engineering. Please see further details below.
Please verify the issue again with FIA wa.7z, which should be final solution candidate.
Root cause:
The power management flow on TGL shut down a clock that is required for exiting from K1 (K1 Is the equivalent of L1 for the proprietary PCIe like interface between the MAC and the PHY).
Due to missing configuration, the clock request was not asserted properly which caused a long K1 exit latency which is the reason for the performance issue.
Solution:
Update the HW MAC initialization flow. Do not gate DMA clock from the modPHY block. Keeping this clock will prevent drop packets sent in burst mode on the Kumaran interface.