On 4/14/2021 10:33 PM, David Coe wrote:
> Hi Suravee!
>
> I've re-run your revert+update patch on Ubuntu's latest kernel 5.11.0-14 partly to check my mailer's 'mangling' hadn't also reached the code!
>
> There are 3 sets of results in the attachment, all for the Ryzen 2400G. The as-distributed kernel already incorporates your IOMMU RFCv3 patch.
>
> A. As-distributed kernel (cold boot)
> >5 retries, so no IOMMU read/write capability, no amd_iommu events.
>
> B. As-distributed kernel (warm boot)
> <5 retries, amd_iommu running stats show large numbers as before.
>
> C. Revert+Update kernel
> amd_iommu events listed and also show large hit/miss numbers.
>
> In due course, I'll load the new (revert+update) kernel on the 4700G but won't overload your mail-box unless something unusual turns up.
>
> Best regards,
>
For the Ryzen 2400G, could you please try with:
- 1 event at a time
- Not more than 8 events (On your system, it has 2 banks x 4 counters/bank.
I am trying to see if this issue might be related to the counters multiplexing).
David,
On 4/14/2021 10:33 PM, David Coe wrote:
> Hi Suravee!
>
> I've re-run your revert+update patch on Ubuntu's latest kernel 5.11.0-14 partly to check my mailer's 'mangling' hadn't also reached the code!
>
> There are 3 sets of results in the attachment, all for the Ryzen 2400G. The as-distributed kernel already incorporates your IOMMU RFCv3 patch.
>
> A. As-distributed kernel (cold boot)
> >5 retries, so no IOMMU read/write capability, no amd_iommu events.
>
> B. As-distributed kernel (warm boot)
> <5 retries, amd_iommu running stats show large numbers as before.
>
> C. Revert+Update kernel
> amd_iommu events listed and also show large hit/miss numbers.
>
> In due course, I'll load the new (revert+update) kernel on the 4700G but won't overload your mail-box unless something unusual turns up.
>
> Best regards,
>
For the Ryzen 2400G, could you please try with:
- 1 event at a time
- Not more than 8 events (On your system, it has 2 banks x 4 counters/bank.
I am trying to see if this issue might be related to the counters multiplexing).
Thanks,
Suravee