Comment 6 for bug 1852723

Thanks Dann,

It's very close.

The root cause is somewhere between these commits and e988af01 is just few commits below.

5d0f174e40a6 <email address hidden> 2019-11-12 19:04:49 +0100 arm64: enable generic CPU vulnerabilites support
f94f9d3a3e8b <email address hidden> 2019-11-12 19:04:49 +0100 arm64: add sysfs vulnerability show for meltdown
c288f6b5788d <email address hidden> 2019-11-12 19:04:48 +0100 arm64: Add sysfs vulnerability show for spectre-v1
f2485ae5fd84 <email address hidden> 2019-11-12 19:04:48 +0100 arm64: fix SSBS sanitization
1931a913df7e <email address hidden> 2019-11-12 19:04:48 +0100 KVM: arm64: Set SCTLR_EL2.DSSBS if SSBD is forcefully disabled and !vhe
fd872fd82e12 <email address hidden> 2019-11-12 19:04:48 +0100 arm64: ssbd: Add support for PSTATE.SSBS rather than trapping to EL3
2a3135c3033c <email address hidden> 2019-11-12 19:04:48 +0100 arm64: cpufeature: Detect SSBS and advertise to userspace
78dc3acb34fa <email address hidden> 2019-11-12 19:04:48 +0100 arm64: Get rid of __smccc_workaround_1_hvc_*
5c43fb65359d <email address hidden> 2019-11-12 19:04:48 +0100 arm64: don't zero DIT on signal return
c6c07232325a <email address hidden> 2019-11-12 19:04:48 +0100 arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening
274adba3ccf6 <email address hidden> 2019-11-12 19:04:47 +0100 arm64: capabilities: Add support for checks based on a list of MIDRs
f34e57c35b72 <email address hidden> 2019-11-12 19:04:47 +0100 arm64: Add MIDR encoding for Arm Cortex-A55 and Cortex-A35
8d811d39465c <email address hidden> 2019-11-12 19:04:47 +0100 arm64: Add helpers for checking CPU MIDR against a range
b2eddaf65384 <email address hidden> 2019-11-12 19:04:47 +0100 arm64: capabilities: Clean up midr range helpers
628859e8621c <email address hidden> 2019-11-12 19:04:47 +0100 arm64: capabilities: Change scope of VHE to Boot CPU feature
3bf4ffd98cc4 <email address hidden> 2019-11-12 19:04:47 +0100 arm64: capabilities: Add support for features enabled early