you could try to flush the endpoint ringing PCI write, and see if it helps
starting the endpint, but I don't have high hopes for this, a PCI write should
be flushed anyway, especially in 25 seconds.
maybe also add trace to re-read the endpoint state after flushing pci write:
(untested)
writel(DB_VALUE(ep_index, stream_id), db_addr);
+ readl(db_addr);
/* The CPU has better things to do at this point than wait for a
* write-posting flush. It'll get there soon enough.
*/
@@ -1176,6 +1177,8 @@ static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
/* if this was a soft reset, then restart */
if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP) ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
+
+ trace_xhci_handle_cmd_reset_ep(ep_ctx);
}
you could try to flush the endpoint ringing PCI write, and see if it helps
starting the endpint, but I don't have high hopes for this, a PCI write should
be flushed anyway, especially in 25 seconds.
maybe also add trace to re-read the endpoint state after flushing pci write:
(untested)
diff --git a/drivers/ usb/host/ xhci-ring. c b/drivers/ usb/host/ xhci-ring. c .20e209b64551 100644 usb/host/ xhci-ring. c usb/host/ xhci-ring. c ep_doorbell( struct xhci_hcd *xhci,
trace_ xhci_ring_ ep_doorbell( slot_id, DB_VALUE(ep_index, stream_id));
index e74518e7de6a.
--- a/drivers/
+++ b/drivers/
@@ -408,6 +408,7 @@ void xhci_ring_
+ readl(db_addr);
/* The CPU has better things to do at this point than wait for a
* write-posting flush. It'll get there soon enough.
*/
@@ -1176,6 +1177,8 @@ static void xhci_handle_
/* if this was a soft reset, then restart */
if ((le32_
+
+ trace_xhci_
}