Comment 33 for bug 1737423

Found some document about size determination in pci devices

had run lspi
jean@jean-Soisy:~$ sudo lspci -vv -k -xxxx -s 03:09.0
03:09.0 VGA compatible controller: NVIDIA Corporation NV44A [GeForce 6200] (rev a1) (prog-if 00 [VGA controller])
 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
 Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
 Latency: 40 (1250ns min, 250ns max)
 Interrupt: pin A routed to IRQ 21
 Region 0: Memory at 94000000 (32-bit, non-prefetchable) [size=16M]
 Region 1: Memory at c0000000 (32-bit, prefetchable) [size=512M]
 Region 2: Memory at 92000000 (32-bit, non-prefetchable) [size=16M]
 [virtual] Expansion ROM at e0000000 [disabled] [size=128K]
 Capabilities: [60] Power Management version 2
  Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
 Kernel driver in use: nouveau
00: de 10 21 02 06 01 b0 02 a1 00 00 03 00 28 00 00
10: 00 00 00 94 08 00 00 c0 00 00 00 92 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 60 00 00 00 00 00 00 00 09 01 05 01
40: 00 00 00 00 02 00 30 00 03 00 00 1f 00 00 00 00
50: 00 00 00 00 01 00 00 00 ce d6 23 00 0f 00 00 00
60: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 01 04 40 c1 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

So, value defines as BAR1 located at adress 0x14 in parameters with value 08 00 00 c0

means : adress is 0xc0000000 with 0x8 = prefetchable

for memory size determination methos is
https://wiki.osdev.org/PCI
https://stackoverflow.com/questions/19006632/how-is-a-pci-pcie-bar-size-determined/39618552#39618552

To determine the amount of address space needed by a PCI device, you must save the original value of the BAR,
write a value of all 1's to the register, then read it back.
The amount of memory can then be determined by masking the information bits, performing a bitwise NOT ('~' in C), and incrementing the value by 1. The original value of the BAR should then be restored.

on my computer : using sudo bless
parameter are located at /sys/bus/pci/devices/0000:03:09.0/config
replaced 08 00 00 c0 by ff ff ff ff then, computer blocked, but was able to read 08 00 00 e0

that means
dropping 4 bits LSB -> 00 00 00 e0
inverting bitwise ff ff ff 10
adding one 00 00 00 20 means 512 M

BUT https://www.xilinx.com/Attachment/PCI_SPEV_V3_0.pdf
6.2.5.1. Address Maps
Devices are free to consume more address space than required

after explanation of a computation method, precision is given

The resultant 32-bit value is the memory/I/O range size decoded by the register.

I Think that the problem is here = adress space decoded, but not populated

Regards

Jean COLIN