* This enables symbols for all device trees built for Xilinx products.
* Currently only device trees which have overlays applied have symbols enabled.
* Most Xilinx device trees are currently overlayed (thus have the symbols already included) so this should have minimal size impact.
[ Test Plan ]
* Xilinx will verify they can load the dtbo's for the FPGA during runtime
[ Where problems could occur ]
* There could be an unexpected impact on other FPGA runtime overlays that are already working.
[ Other Info ]
* Xilinx platforms apply dtbo's during runtime when loading FPGA firmware.
[ Impact ]
* This enables symbols for all device trees built for Xilinx products.
* Currently only device trees which have overlays applied have symbols enabled.
* Most Xilinx device trees are currently overlayed (thus have the symbols already included) so this should have minimal size impact.
[ Test Plan ]
* Xilinx will verify they can load the dtbo's for the FPGA during runtime
[ Where problems could occur ]
* There could be an unexpected impact on other FPGA runtime overlays that are already working.
[ Other Info ]
* Xilinx platforms apply dtbo's during runtime when loading FPGA firmware.